SEH can offer polished wafers manufactured with standard CZ crystal technology. The 200MM polishing process can be optimized to meet the flatness requirements of leading edge design rules ( to 90nm or below ).
Standard CZ technology suffers from the problem of high COP levels. Vacancy related crystal defects such as COP/FPD (Crystal Originated Pits/Flow Pattern Defects) can cause near surface problems during device manufacture. Examples of the device problems associated with these defects are poor GOI (TZDB, TDDB) and current leakage in P-N Junctions. COPs are 0.1-0.2µm octahedral shaped voids with walls covered by oxide. FPD is a vacancy cluster related defect exposed by preferential etching.
The general trend is that standard CZ wafers are appropriate for design technologies greater than 180nm, while more advanced technologies are generally considered at 180nm design rules and below.
See also our Epi, Annealed Wafer and Low Defect Crystal offerings.